Recent high performance logic systems are getting larger and larger and more and more complicated as the simlicon technology improves dramatically. As a matter of fact, the time to verify the correctness of a logic circuit has been getting longer and more important than the time to design to develop such a logic chip. In terms of emulation speed, logic emulation with haredware is much preferable to with software. Although hardware emulation has already been used for verification, building an emulator for large logic system in a conventional way is as expensive as hundreds of thousands or even millions of dollars.
DIMES hires an FPGA (or a few FPGAs) for the central of logic emulation in its emulation unit. Our emulation target is a large logic design such as a multiprocessor system on chip(MpSOC) or cellular architecture chip, such that it can not fit into a small number of FPGAs straightforwardly. Our iterative emulation technique makes large scale emulation possible by folding a repetitive module, such as multiprocessor, into a single piece of repetition. State sets in every piece are stacked up on the single piece of the module. DIMES iteratively emulates each piece of the module by replacing its state set at every iteration cycle. Taking the number of iteration cycles with which every piece is emulated one time each, the system obtains a whole virtual emulated cycle, with a compromized emulation speed, which is still much faster than emulation by software. This idea is not only limited to a single chip but applicable to a multichip system by using plenty of memory holding the state sets. Also, the performance scales by partitioning the targeted design into multiple emulation units of DIMES. Therefore, DIMES emulates a large logic design such that an FPGA can not hold with a straightforward way, with an FPGA at the lowest cost or with several FPGAs for a higher speed.
The DIMES project team, in the Computer Architecture and Parallel Systems Laboratory(CAPSL) of University of Delaware, has started to study this method of emulation and to develop DIMES hardware and software since 2002.
The first emulation target of DIMES is the IBM Blue Gene/Cyclops architecture. The Cyclops chip contains a number of processors and is appropriate to demonstrate iterative emulation with small number of FPGAs. We have been developing a Cyclops emulator and its software on DIMES now.