Resume
Table of Contents
Section A: Teaching and Research Supervision
A.1 TeachingSection B: Scholarship
B.1: Research Activity and InterestsSection C: Services
C.1 University Activities and ServicesCURRICULUM VITAE
NAME: Guang R. Gao
OFFICE ADDRESS:
Department of Electrical Engineering
104 Evans Hall
University of Delaware
Newark, DE 19716
Tel: 302-831-8218
Fax: 302-831-4316
ggao@eecis.udel.edu
EDUCATION
Ph.D Degree in Electrical Engineering and Computer Science
Massachusetts Institutes of Technology, August 1986.
Member of Computational Structures Group at Laboratory of Computer Science, MIT,
June 1982 to August 1986.
Master Degree in Electrical Engineering and Computer Science
Massachusetts Institutes of Technology, June 1982.
BS in Electrical Engineering
Tsinghua University, Beijing.
PROFESSIONAL EXPERIENCE
University of Delaware
Newark, DE.
Associate Professor, Department of Electrical and Computer Engineering, Sept. 96-present
Associate Professor, Department of Electrical and Computer Engineering, Sept. 96-present
Founder and a leader of the Computer Architectures and Parallel Systems Laboratory (CAPSL) .
McGill University
Montreal, Canada
Associate Professor, School of Computer Science, June'92-August,1996
Assistant Professor, School of Computer Science, Aug.'87-June'92
Founder and a leader of the Advanced Compilers, Architectures and Parallel Systems Group (ACAPS) at McGILL since 1988.
Philips Research Laboratories
Sept. 1986 - June 1987
Briarcliff Manor, NY, USA
Senior member of research staff of the Computer Architecture and Programming Systems Group. Played a major role in founding a multiprocessor system project, and research in parallelizing compilers.
Massachusetts Institutes of Technology
June 1980 - Aug. 1986
Member of the Computational Structures Group at the Laboratory of Computer Science, MIT. Participated in the MIT Static Dataflow Architecture Project and other projects.
Proposed a novel methodology of organizing array operations to exploit the fine-grain parallelism of dataflow computation models. Developed a unique pipelined code mapping scheme for dataflow machines (later known as dataflow software pipelining).
Center Of Advanced Studies, IBM Toronto Lab
Aug 1993 - June 1994
Visiting scientist with a NSERC Senior Industrial Fellowship.
CURRENT RESEARCH AREAS:
Computer Architecture and Systems
Parallel and Distributed Systems
Optimizing and Parallelizing Compilers, Parallel Programming
VLSI and Application-Specific System Design
PROFESSIONAL MEMBERSHIP
I am a Senior Member of IEEE, Member of ACM, ACM-SIGARCH, ACM-SIGPLAN.
I am currently a Distinguished Visitor of IEEE Computer Society.
NATIONAL RECOGNITION:
I have given seminars in many industrial and academic organizations: IBMT.J. Watson Research Center, IBM Toronto Lab, AT&T Bell Laboratories, BNR, HP Labs, SGI, DEC, NRL(Navy Research Lab.), MIT, Stanford, UC Berkeley, NYU, Cornell U., University of Victoria are just named a few.
Section A: Teaching and Research Supervision
A.1 Teaching
A.1.a Teaching at University of Delaware
CPEG 324 Computer System Design
This is is a new undergraduate CE design course which I developed and taught in Spring 97. Now, it will be offered again under the title CPEG-422 this fall.
This course stresses the principal design concepts which are embodied in modern computer architectures, and emphasizes ideas which we believe will continue to apply into the future, in spite
of a rapidly changing technological environment. The primary objective of the course is to show how the design and evaluation of architectural features, based on both qualitative and quantitative studies, can be used to achieve balanced, efficient systems, well-matched to the class of problems they overcome.
ELEGG-652: Topics in High-Performance Architecture
This is a graduate core course and I taught it first time in the fall of 1997.
This course examines the basic principles and methodology used in the design and evaluation
of high-performance computer architectures, and its relation with the underlying program execution and architecture models. Topics include pipelining and vector processing, instruction level parallelism (ILP) architectures, multiprocessor architectures and high-speed networking, memory consistency models and cache-coherence issues, fine-grain parallelism and multithreaded architectures, and the roles of optimizing and parallelizing compilers.
ELEG 867-14: Topics in Hardware/Software Codesign
This new course introduces the concepts, principles and methods of digital system design from both a hardware and a software viewpoint. In the context of general purpose computer systems, the principles studied in this course include the close interaction between compiler technology and architecture design. In the context of special-purpose systems, such as embedded systems, the course will deal with the close interaction between software synthesis and hardware system design.
Topics to be discussed include the fundamentals of analysis, generation, synthesis, and optimization of computer code. Specific topics in this area include dependency analysis, code motion,
scheduling, register and resource allocation. Among the hardware micro-architecture topics studied are pipeline co-design and memory models. Important case studies that illustrate the basic principles
of software/hardware co-design will be introduced. Topics in the new emerging field of adaptive computing system design will be discussed.
- New hardware/software tools introduced or developed for teaching laboratories:
Modern computer architecture and system design involve both intensive software and hardware design activities. In the new courses introduced, the students are exposed to both software/hardware tools and methodology for computer architecture design (e.g. software simulation toolset) as well as hardware design tools and methodology (e.g. VHDL tools and environments) on digital systems.
Students are expected to learn modern design tools and related skills through lab assignments and course projects. To this end, we have invested extensive effort to develop the laboratory and introduce the VHDL design environment in the course.
- The CAPSL laboratory seminar series.
I have established the Computer Architecture and Parallel System Laboratory since I joined UDel. In addition to perform research, one important objective of this laboratory has been to facilitate the teaching of the computer architecture and digital system courses, and training of graduate research and teaching assistants. The new courses and software tools described above depend directly on this laboratory. The laboratory is now equipped with various workstations, We have a wide variety of research and teaching software installed, and a number of my best graduate students have been actively participated and contributed to teaching. Activities organized include:
A.1.b Other Teaching Experience
At McGill Uniersity, I have introduced and developed a set of new courses (308-505,308-605,308- 622) on high-performance computer architectures, parallel systems and parallelizing compilers. These courses have been consolidated and improved over the period of time, forming a core for students who are interested in the related subject areas. I have also taught a number of graduate seminar courses. (Details can be provided by request). The excellence of my teaching have been recognized through the following outstanding teaching award nominations:
A.2. Research Supervision
Current, graduate students under my supervision include:
Gieger, Thomas (processing in memory and multithreading)
Marquez, Andres (multithreaded architectures)
Ryan, Sean (optimizing compilers)
Stouchinin, Artour (instruction-lelvel parallelism, software pipelining)
Tang, Xi-Nan (compiler for multitheading)
Thulasiraman, Parimala, (parallel algorithmsand applications)
Yang, Hongbo (instruction-level parallelism)
Douillet, Alban (compiling for multithreading)
Current Postodoc fellows under my supervision include:
Amaral, Nelson (system software, compilers)
Kevin, Theobald (computer architecture, parallel systems)
Rupak, Thulasiram (parallel applications)
Already Completed:
The applicant has completed the supervision of 7 Ph.D. and 18 M.Sc. students, and 5 postdoctoral fellows in the proposed research areas of high-performance computing.
Post-Doctor |
Ph.D. Level |
M.Sc Level |
||||
(4 Completed) |
(7 Graduaged) |
(18 Graduated) |
||||
G. Liao |
E. Altman |
(1991 - 1996) |
H. Cai |
(1995 - 1997) |
R. Shanker |
(1991 - 1993) |
(1991-1993) |
H. Hum |
(1998 - 1992) |
N. Elmasri |
(1992 - 1995) |
N. Shiri |
(1990 - 1992) |
O. Maquelin |
S. Nemawarka |
(1989 - 1996) |
A. Emtage |
(1988 - 1991) |
R. Silvera |
(1996 - 1997) |
(1994 - 1998) |
Q. Ning |
(1990 - 1993) |
S.H. Han |
(1996 - 1997) |
A. Stouchinin |
(1994 - 1996) |
G. Ramaswamy |
V. C. Sreedhar |
(1990 - 1995) |
A. Jimenez |
(1993 - 1996) |
R. Wen |
(1993 - 1995) |
(1990 - 1994) |
G. Tremblay |
(1988 - 1994) |
L. Lozano |
(1992 - 1994) |
Y-B Wong |
(1989 - 1991) |
X. Tian |
R. Yates |
(1988 - 1992) |
S. Merali |
(1993 - 1996) |
|
|
(1993 - 1996) |
C. Moura |
(1991 - 1993) |
||||
J. Wang |
C. Mukerji |
(1991 - 1994) |
||||
(1995 - 1997) |
R. Olsen |
(1989 - 1992) |
||||
Z. Paraskevas |
(1987 - 1989) |
|||||
H. Petry |
(1995 - 1997) |
Those who have graduated are highly trained in the field of parallel architectures and compilers, as evidenced by the fact that they have been working (or worked) as tenure-track university professors (Ramaswamy, Tremblay); as engineers in key industrial sectors, e.g., Intel(Hum), Nortel (Wang), IBM (Altman,Nemawarkar, Sreedhar), BNR (Liao, Wen), HP (Lozano), Convex (Ning), NCUBE (Olsen), CAE(Nassur), AT&T (Petry); and as researchers in government labs, e.g., LLNL (Yates), or assuming other professional jobs.
Section B: Scholarship
B.1 Research Activity and Interests
1. Computer Architecture and Systems.
One main question facing modern computer architects is: Is it ever possible to build a high-performance parallel architecture combining the power of hundreds, or even thousands, of processors to solve real world applications (regular or irregular) with scalable performance?
My research interests have been seeking an answer to this challenge. In particular, our primary work has been concentrated on multithreaded program execution models and architectures. To this end, I have initiated/led or played a major roles in a number of research projects in this area.
2. Optimizing compiler technology.
has been conducted. Currently, we are extending our method and studying new thread partitioning algorithms which can integrate the scheduling and register allocation under the same framework
(partially funded via a NSF-CCR grant).
3. Other areas
protocol based on such a memory model. I and my colleague have defined a new memory consistency model, called Location Consistency (LC), in which the state of a memory location is modeled as a
partially ordered multiset (pomset) of write and synchronization operations. We have proved that LC is strictly weaker than existing memory models, but is still equivalent to stronger models for parallel
programs that have no data races. We also introduced a new multiprocessor cache consistency protocol based on the LC memory model.
B.2: List of Research Contributions
Refereed Journal Publications
X. Tang and Guang R. Gao, Automatic partitioning threads for multithreaded architectures, Special Issues on Compilation and Architectural Support for Parallel Applications, Accepted for Application, June, 99.
Publications in Refereed Conference Proceedings (Last Six Years Only)
I have more than 80 publications in refereed conferences. Due to space limitations, only those in the last 6 years are listed. The rest can be provided by request.
Monographs, Books and Book Chapters
B.3 Research Significance
The theme of my research in computer architecture and systems, compiler technology, and memory models not only enriches the field of parallel computing and encompass a host new techniques for high-performance architectures and compiling technology but also provides a new horizon for mapping applications, both regular or irregular, onto these architectures. Furthermore, the research activities are not only themselves intellectually stimulating, interesting and competitive, but also exposes students with a dynamic new field with excellent prospect of
employment and a productive career.
My work on EARTH model and architecture has important relevance to the design and development of future generation of parallel computer architectures. The research results have been published widely in a range of recognized international professional conferences and journals. It has attracted a considerable level of research support from NSF through 4 NSF research grants encompassing the areas from architecture and memory support, the efficient implementation of multithreaded execution models on SMP workstation cluster based parallel systems, the application of EARTH model to large irregular applications such as the crack propagation problem, and the compilation technology for multithreading. It has also attracted industry interests and funding such as the DRP grant we received with support from ACORN Inc. An extension of our work on fine-grain multithreading and EARTH to be applied to high-end Supercomputing has become an important component to the HTMT project, one of the few nation's on-going petaflow architecture project funded by DARP, NSA and NASA.
My work on modulo scheduling and software pipelining also have immediate relevance to the computer industry in their effort to exploit high performance with instruction level parallelism.
The research results have been published widely in a range of recognized international professional conferences and journals. The technology developed in our group has been used in the evaluation of the software pipelining techniques in the SGI production compiler,
and to foster the future collaboration, we have received the donation of two SGI workstations with special SGI software.
The co-scheduling technique has been funded by NSF through a research grant. The co-scheduling technology developed by me and my colleagues have also attracted strong industry attention, and Rockwell Semiconductor Systems has already committed funding to this research and a DRP grant on retargetable compiler for DSP architectures with Rockwell funding and
university matching has just been awarded.
The significance and novelty of my work on program analysis and memory models have also been recognized by the research community. Three papers out of the work on program
Analysis have been accepted for publications on the most prestigious journal -- the ACM Transactions on Program Languages and Systems.
B.4 Research Support
Agency | Grant Number | Title | Amount | Period | Status |
NSF | CCR 9808522 | Compiling Irregular Applications on a Multithreaded Architecture | $319,156 | 08/97 - 07/00 | co-PI |
NSF | MIPS 9707125 | A New Generation Multithreaded Processors | $400,000 | 07/97 - 06/00 | co-I |
NSF | CDA 9703088 | Parallel and Distributed Computing: Systems and Applications Development | $633,513 | 07/97 - 06/02 | co-PI |
(Infrastructure Grant) | |||||
DARPA/NSA/NASA | ASC 9612105 | Hybrid Technology Multithreaded Architecture for Petaflops | $800,000 | 06/97 - 05/99 | co-I |
NSF | CCR 971147 | A Framework of Modulo Scheduling Based on Finite Automaton | $139,263 | 06/97 - 05/99 | PI | (with REO) | $6,250 | 06/97 - 05/98 |
DRP | Approved | Retargetable Compilers for Embedded DSP Processors | $75,000 | 98-00 | PI |
(with Rockwell Semiconductor Systems Inc.) |
Section C: Services
C.1 University Activities and Services
C.2 Profession Services
I have served as a workshop chair, a session chair, an organizing committee or steering committee member of many international conferences.
I have given seminars in many industrial and academic organizations: IBMT.J. Watson Research Center, IBM Toronto Lab, AT&T Bell Laboratories, BNR, HP Labs, SGI, DEC, NRL(Navy Research Lab.), MIT, Stanford, UC Berkeley, University of Victoria are just named a few.