A memory consistency model
represents a binding ``contract'' between software
and
hardware in a shared-memory multiprocessor system.
It is important
to provide a memory consistency model that is
easy to understand and that also facilitates efficient implementation.

The memory consistency model that has been most commonly used in past work
is {\it sequential
consistency} (SC), which requires the execution of a parallel
program to appear as some interleaving of the memory operations
on a sequential machine.
To reduce the rigid constraints of the SC model, several
relaxed consistency models have been proposed, notably
{\it weak ordering} (or {\it weak consistency}) (WC), {\it release
consistency} (RC), {\it
data-race-free-0}, and
{\it data-race-free-1}.
These models allow performance optimizations to be correctly applied,
while guaranteeing that sequential consistency is retained
for a specified class of programs.
We call these models {\em SC-derived} models.
A central assumption in the definitions of all
SC-derived memory consistency models is the
{\em memory coherence} assumption, which can be informally stated as
follows~\cite{GharachorlooEtAl90}:
``all writes to the same location
are serialized in some order and are performed in that order
with respect to any processor''.

In this paper, we propose a {\it location consistency} (LC) model for
memory consistency.
A distinguishing feature of the LC model is that it
does not rely on the
assumption of memory coherence.
Instead of assuming that all writes to the same location
are serialized according to some total order, we model
the state of a memory
location as a partially ordered multiset (pomset) of write operations
and
synchronization operations.
The partial order in the pomset
naturally follows from
the ordering constraints  defined by a concurrent program and its execution.
The LC model provides a very simple ``contract'' between
software and hardware;
only the partial order defined by the program
needs to be obeyed, and there is no requirement for all processors to
observe the same ordering of concurrent write operations.
Further, concurrent
asynchronous reads and writes to the same memory location are
well-defined in the LC~model, rather than being considered as error conditions.
We demonstrate that the LC model allows more compiler and hardware
performance
optimizations to be applied, compared to the other memory consistency
models mentioned above.  The LC model is also easier to implement
because the serialization constraints imposed by SC and SC-derived
models (e.g. due to the memory coherence assumption) are removed.
