I have contributed to the training of a number of Ph.D and M.Sc. students, and post-doctoral fellows in the proposed research areas of high-performance computing, and towards providing new knowledge to the field through publications and presentations in conferences, workshops and seminars. The following personnel have been trained under my supervision.

Past Post-Doctoral Fellows

Name Period Whereabouts
G. Liao
1991-1993
Deceased
O. Maquelin
1993-1997
Intel
G. Ramaswamy
1990-1994
IIS (Indian)
X. Tian
1993-1996
Intel
J. Wang
1995-1997
Nortel
Jose. H. Amaral
1998-2000
U of Alberta
Benoit Dupont de Dinechin
1995-1996
CEA, France
Ruppa Thulasiram
1997-2000
U. of Manitoba
Gerd Heber
1997-1999
Cornell
Chihong Zhang
1998-1999
Conexant
Rongcai Zhao
2000-2001
China
Jianshan (Jason) Tang
2001-2003
GlaxoSmithkline Pharmaceuticals

Current Post-Doctoral Fellows

Name Area
Ziang Hu
Compilers
Jizhu Lu
Parallel Systems
Haiping Wu
Compilers
Hongbo Rong
Compilers
Hirofumi Sakane
Computer Architecture, VLSI Design
Jozsef Bukszar
Bioinformatics

Past Ph.D. Students

Power-Aware Compilation
Name Thesis Title Graduation Whereabouts
H. Hum The Super-Actor Machine: A Hybrid Dataflow/von Neumann Architecture
1992
Intel
R. Yates Semantics of Timed Dataflow Networks
1992
Lawrence Livermore Lab.
Q. Ning Register Allocation for Optimal Loop Scheduling
1993
CENVEX
G. Tremblay Parallel Implementation of Lazy Functional Languages Using Abstract Demand Propagation
1994
U. of Quebec
E. Altman Optimal Software Pipelining with Function Unit and Register Constraints
1996
IBM
V. C. Sreedhar Efficient Program Analysis Using DJ Graphs
1995
IBM
S. Nemawarkar Performance Modeling and Analysis of Multithreaded Architectures
1996
IBM
Kevin Theobald {EARTH}: An Efficient Architecture for Running Threads
1999
Intel
Xinan Tang
1999
Parimala Thulasiraman Irregular Computations on Fine-Grained Multithreaded Architecture
2000
U. of Manitoba
Hongbo Yang Instruction-Level Parallelism
2003

Current Ph.D. Students

Name Area
A. Marquez Multithreaded Architectures
A. Stoutchinin Instruction-Level Parallelism, Software Pipelining
Alban Douillet Compiler Optimizations for Multi-Threaded Architectures
Praveen Thiagarajan Bioinformatics & Visualization
Rishi Khan Computational Biology & HPC
Robel Y. Kahsay Computational Biology & HPC
Juan del Cuvillo Computer Architecture
Yanwei Niu Bioinformatics
Weirong Zhu Parallel Systems
Mihailo Kaplarevic Computational Biology & HPC
Levent Yakay Architecture
Yuan Zhang Compilers

Past Masters Students

From McGill University

Name Thesis/Project Title Graduation Whereabouts
R. Tio Instruction set Definition for the Argument-Fetching Dataflow Machine
incomplete
CISCO System
Z. Paraskevas Code Generation for Dataflow Software Pipelining
1989
Greece
J-M Monti Interprocessor Communication Supports for A Multiprocessor Dataflow Machine
1991
France
E. Altman Genetic Algorithms and Cache Replacement Policy
1991
IBM
Y-B. Wong A Petri-Net Model for Loop Scheduling
1991
McGill
A. Ematage n/a
1991
Bunyip Information
R. Olsen Collective Analysis and Transformation of Loop Clusters
1992
nCube
N.Shiri A Design and Implementation of Unimodular Transformations of Loops
1992
Concordia University
R. Shanker Parallel A*-Viterbi for Speech Recognition
1993
Australia
C. Moura A Generic Superscalar Simulator
1993
France
C. Mukerji Register Allocation Using Cyclic Interval Graphs
1994
n/a
L. Lozano Exploiting Short-Lived Variables in Superscalar Processors
1995
HP
R. Wen The Design and Implementation of an Accurate Array Data-Flow Analyzer in the HPC Compiler
1995
BNR
N. Elmasri TCL: Experiences on a multiprocessor with dual-processor nodes
1996
Montreal
A. Jimenez Paraffins on Earth: An Implementation of Paraffins Based on Threaded-C
1996
AES
S. Merali Designing and Implementing Memory Consistency Models for Shared-Memory Multiprocessors
1996
DPW-Lawyer
A. Stoutchinin Integer Linear Programming Based Software Pipelining and Register Allocation Scheme for a Superscalar Microprocessor
1996
UDel
H. Cai Dynamic Load Balancing
1997
Intel
Raul Silvera
1997
IBM Toronto
S.H. Han Cache Analysis
1997
Intel
H. Petry Comparison of SC Derived Memory Models and Location Consistency on Shared Memory Architectures
1997
McGill
R. Munoz Static Instruction Scheduling for Dynamic Issue Processors
1997
McGill
D. Tarlescu A study of correlation-based branch prediction schemes
1998
Montreal
Kamala Prasad Kakulavarapu Dynamic Load Balancing Issues in the {EARTH} Runtime System
2000
Intel
L. Boulianne WWW Caching Analysis
McGill

From University of Delaware

Name Thesis/Project Title Graduation Whereabouts
Ian Walkar
1999
Intel
Cheng Li
1999
Florida
Lei Liu
1999
Cisco
Sean Ryan
2001
Intel
Christopher Morrone
2001
Lawrence Livermore Lab.
Juan del Cuvillo
2001
Pursuing Ph.D at UDel
Alban Douillet
2001
Pursuing Ph.D at UDel
Praveen Thiagarajan
2001
Pursuing Ph.D at UDel
Rishi Kumar
2001
Qualcomm
Mohamed Mostagir
Bioinformatics

Current Masters Students

Name Area
Tamal Basu Compilers
Chuan Shen Parallel Systems
Fei Chen Network Processors
Kapil Khosla Compilers
Anand Kulkarni Parallel Systems
Madhuri Boddu Parallel Systems
Yan Xie Compilers
Xing Wang Bioinformatics
Vishal Karna VLSI Design

Those who have graduated are highly trained in the field of parallel architectures and compilers, as evidenced by the fact that they have been working (or working) as tenure-track university professors (Ramaswamy, Tremblay); as enginners in key industrial sectors, e.g., IBM (Altman, Nemawarkar), BNR (Wen), HP (Sreedhar, Lozano), Convex (Ning), NCUBE (Olsen), Intel(Hum); and as researchers in government labs, e.g. LLNL (Yates), or assuming other professional jobs.
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